In the semiconductor industry, there is a continuing trend toward high device densities. To achieve these high device densities, small features on semiconductor wafers are required. These features include source regions, drain regions, and channel regions that relate to devices, such as field effect transistors (FETS).
In the process of scaling down complementary metal oxide semiconductor (CMOS) devices, which are a type of FET, a vertical dimension must be reduced at the same time as horizontal dimensions are reduced. In particular, source and drain regions, or at least source drain extension regions adjacent the channel, must be made extremely shallow, with a corresponding increase in doping, in order to avoid short channel effects. For example, the source/drain extension regions adjacent the channel of a 0.1 μm CMOS device must be no more than about 50 nm thick and have a dopant concentration of about 5×1019 atom/cm3 or greater.
The formation of ultra-shallow junctions, that is, junctions having source/drain regions no more than about 50 nm thick, is considered one of the significant challenges in manufacturing the next generation of CMOS devices. The usual approach to forming source/drain regions is ion implantation. A recognized shortcoming of ion implantation is that it produces interstitial atoms that can greatly enhance (10 to 1000 times) the diffusivity of dopants. Enhanced diffusivity causes undesirable spreading of the dopants during thermal annealing that is carried out to repair the crystal structure of the substrate after doping.
Fluorine co-implants have been tried as an approach to reducing the enhanced diffusivity caused by ion implantation used to incorporate the dopant atoms. This has been found to be partially successful in mitigating the enhancement caused by ion implantation Higher temperatures raise the diffusivity and offset the benefit of the co-implants. Thus, there remains an unsatisfied need for effective methods of forming ultra-shallow junctions.